A programmable logic device (PLD) is a general-purpose device that can be programmed by a user to implement a variety of selected functions. One type of PLD is the field programmable gate array (FPGA), which typically includes an array of configurable logic blocks (CLBs) surrounded by a plurality of input/output blocks (IOBs). The CLBs are individually programmable and can be configured to perform a variety of logic functions on selected input signals. The IOBs can be configured to drive output signals from the CLBs to external pins of the FPGA and/or to receive input signals from the external FPGA pins.
The FPGA also includes a programmable interconnect structure that can be programmed to selectively route signals among the various CLBs and IOBs to produce more complex functions of many input signals. The CLBs, IOBs, and programmable interconnect structure are programmed by loading configuration data into associated configuration memory cells that control various switches, multiplexers, and look-up tables (LUTs) within the CLBs, IOBs, and programmable interconnect structure to implement logic and routing functions specified by the configuration data. As such, FPGAs inherently provide a high degree of configurability and are, therefore, ideally suited for a plurality of hardware applications.
For example, FPGAs are ideally suited for the implementation of an I/O interface that is capable of supporting a large number of input/output (I/O) interface standards. For example, many modern processing systems operate according to the peripheral component interconnect (PCI) standard, which among other features, defines a specification for attaching peripheral devices to a computer mother board. In other examples, modern processing systems may also utilize the high speed transceiver logic (HSTL) standard for data transfers to and from memory, and/or the low-voltage differential signaling (LVDS) standard for backplane communications.
As each new I/O standard is introduced, a corresponding specification is published to define I/O signal parameters, e.g., voltage out high (VOH), voltage out low (VOL), rise-time, fall-time, duty cycle, etc., that conform to the new I/O standard. In addition, output driver behavior during various non-operational modes of the I/O interface may also be defined. For example, the PCI33 and PCI66 specifications dictate certain behavior that must be exhibited by an I/O interface when the I/O interface is operating in a tri-state mode, i.e., when the I/O interface is non-conductive.
In particular, the PCI33 and PCI66 specifications require that in the event an external transient voltage exceeding the operational voltage magnitude, e.g., VCCO, of the I/O interface is applied to the I/O interface during the tri-state mode, then the I/O interface must transition from the tri-state mode to a conductive mode. In such an instance, the I/O interface must be sufficiently conductive so as to “clamp” the over-voltage magnitude to a magnitude that is substantially equal to VCCO. Once the over-voltage condition subsides, the I/O interface transitions back to the tri-state mode.
The ability to clamp over-voltage conditions to VCCO, however, conflicts with another requirement of the I/O interface. In particular, hot-socketability, also referred to as hot-swappability, is the ability to electrically and mechanically engage a non-powered, fully populated printed circuit board to an interface, such as a computer mother board, that is powered and functional. Such an operation is consistent with the universal serial bus (USB) specification, for example, whereby any USB device may be connected to an operational computer via a standardized interface socket, such that the USB device becomes interoperable with the computer without the need to re-boot the computer.
Such a plug-and-play operation, however, is not consistent with the over-voltage clamp requirement because certain conduction paths within the I/O interface must be eliminated in order to conform to the hot-swappable functionality. In other words, the I/O interface must be conductive during an over-voltage condition in order to conform to the PCI33/PCI66 specification, but must also be non-conductive in order to conform to the USB specification for hot-swappability.
Efforts continue, therefore, to provide an I/O interface that may be configured to conform to the requirements of one I/O standard and reconfigured to conform to the conflicting requirements of another I/O standard.